Customers of semiconductor products are continually demanding smaller and smaller semiconductor devices. A semiconductor package accounts for a significant portion of the overall semiconductor device size. Ideally many customers would like to receive a bare silicon die as opposed to a packaged die. While semiconductor manufacturers would like to supply customers with bare silicon die, they are faced with the problem known as the "Known Good Die" (KGD) problem. As semiconductor manufacturers work to supply customers with bare silicon die, a method for insuring proper device operation at the die level is necessary. Yet at this time, a testing procedure for testing full functionality of unpackaged semiconductor die is not available. Until the KGD problem is solved, semiconductor manufacturers are forced to package individual semiconductor die into testable packages which are as close to the die size as possible.
Semiconductor packages which are currently available and are accepted as industry standards generally do not accomplish the goal of having the final package device be as close in size to the semiconductor die as possible. For example, traditional transfer molded plastic packages with metal lead frames are on the order of six to sixty times larger than die that are packaged inside. Ceramic or molded Pin Grid Array (PGA) devices are on the order of four to ten times larger than the die packaged inside.
An emerging package which has achieved a significant reduction in the final package size as compared to the die size is an Over-Molded Pad Array Carrier (OMPAC) package, also known as a plastic Ball Grid Array (BGA) package. As presently manufactured, plastic BGAs are on the order of two to eight times larger than the semiconductor die packaged inside. While BGAs have achieved a significant reduction in the final package device size, they are limited by the manufacturing processes used to make both the die and the package. For example, although the conductive traces and pads on a BGA substrate can be lithographically defined to achieve a very fine pitch, the bond pad pitch on the semiconductor die is typically restricted from achieving a comparable pitch due to spacing and design rules used to account for wire bonding methods and tolerances, such as capillary tool interference during wire bonding. The bond pad pitch accordingly restricts further reductions in the package substrate size. Another limitation to bond pad and conductive trace pitch relates to the problem of wire sweep caused by the transfer molding process. Bonding wires which are used to electrically connect the bond pads of the die to the conductive traces of the substrate may be deformed during the molding process as the molding compound flows across the die and the package substrate. The sweeping of the wires during a molding process may be so severe so as to cause electrical shorts between adjacent wires. Making the traces and bond pads farther apart reduces the adverse affects of wire sweep.
Accordingly, a need exists for a packaged semiconductor device having an overall size closer to the die size in existing semiconductor packages without many of the disadvantages present in existing packages. Specifically, this need exists for semiconductor devices having a large number of input and output terminals, because such devices traditionally have package sizes much larger than the semiconductor die and correspondingly large packages.